Jury

Thesis Director
Mr. Farid MEDJDOUB CNRS scientist(IEMN, France)
Mr. Christophe Detavernier Professor (University of Ghent, Belgium)

Reviewers
Mr Rachid Driad Senior scientist (IAF, Germany)
Mr Jerome Billoue Professor (University of Tours, France)

Examiners
Mrs. Nathalie Malbert Professor (IMS, France)
Mr. Benoit Bakeroot Professor (University of Ghent, Belgium)

Invited
Jean-Francois Rolinat Program manager (STMicroelectronics, France)
Thierry Boudet Program manager (Soitec, France)

Summary:

This thesis explores the development of new GaN-on-silicon vertical power devices, aiming to achieve high performance in the 600 to 1200 V range with operational reliability, including avalanche breakdown capability. With the increasing energy demands of modern society, it is becoming imperative to develop more efficient power electronics. Traditional silicon-based devices have reached their physical limits, prompting the search for alternative materials. Gallium nitride (GaN) is proving to be a promising solution due to its superior physical properties and reduced manufacturing cost when grown on a silicon substrate. The research begins with a comprehensive review of the current state of the art of GaN devices on silicon, highlighting the need for vertical architectures over traditional lateral designs. The use of vertical devices is motivated by their ability to improve reliability, particularly with respect to high-voltage breakdown behaviour.
Simulation studies using Silvaco software were carried out to optimise the design of GaN P-I-N diodes on silicon, in order to improve on- and off-state performance. The thesis also addresses the fabrication processes, discussing the optimisation of ohmic contacts, mesa formation, edge termination and buffer layer etching. Techniques such as polyimide passivation and thick copper heat sinks were employed to improve thermal management and mechanical stability.
Key results include a significant reduction in leakage current and improved diode off-state performance thanks to advanced epitaxial growth techniques and innovative buffer layer designs. The first demonstration of avalanche breakdown in vertical GaN devices on silicon substrate is presented, achieving a high voltage withstand of up to 1200 V. In addition, a TMOSFET pseudo-vertical transistor in GaN on silicon has been developed, demonstrating promising preliminary performance.
This work lays the foundations for future progress in GaN technology on vertical silicon, highlighting its potential in terms of the performance/cost ratio for future applications in power electronics.

Abstract:

This thesis explores the development of novel vertical GaN-on-Silicon power devices, aiming to achieve high performance in the 600-1200 V range with reliable operation, including avalanche capability. As modern society's demand for energy grows, there is an urgent need for more efficient power electronics. Traditional silicon-based devices have reached their physical limits, driving the search for alternative materials. Gallium Nitride (GaN) presents a promising solution due to its superior physical properties and cost-effectiveness when grown on silicon substrates.
The research begins with a comprehensive review of the current state of GaN-on-Silicon devices, highlighting the need for vertical configurations over traditional lateral designs. The use of vertical designs is motivated by their ability to enhance reliability, particularly in terms of breakdown behavior at high voltages.
Simulation studies using Silvaco software were conducted to optimize the design of GaN-on-Silicon P-I-N diodes, targeting improved performance in both on-state and off-state conditions. The thesis also delves into the fabrication processes, discussing the optimization of ohmic contacts, mesa formation, edge termination, and buffer layer etching. Techniques such as polyimide passivation and thick copper heatsinks were employed to enhance thermal management and mechanical stability.
Key findings include a significant reduction in leakage current and improved off-state performance through advanced epitaxial growth techniques and innovative buffer designs. The first demonstration of avalanche capability in vertical GaN devices on silicon substrates, achieving high breakdown voltages up to 1200 V, is presented. Additionally, a pseudo-vertical GaN-on-Silicon trench MOSFET was developed, demonstrating promising initial performance metrics.
This work lays the groundwork for further advancements in GaN-on-Silicon technology, highlighting its potential as a cost-effective, high-performance solution for future power electronic applications.
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