This activity is related to the envisaged end of Moore’s law. ITRS (now IRDS) suggests replacing the Silicon channel in by III-V material in N-MOSFET.  The idea is to compensate the reduction of supply voltage V_DD necessary to low power consumption, by the improvement of electron mobility (i.e. the effective mass). Indeed better transport could allow same I_ON with a lower V_DD. This activity was founded by ANR P2N MOSINAS in collaboration avec le LETI, le LTM, STmicorelectronic, l’IEF et l’IMEP. IEMN was coordinator. We have been also partners in the framework of STREP project Compose3D. The issue of the project was to develop III-V technology compatible with 300mm Silicon platform. Functional III-V MOSFETs have been developed as part of this project. A strong collaboration with Epiphy group allows relevant technological step on localized selective Molecular Beam Epitaxy (LS-MBE) leading to self aligned MOSFET (Figure 6). The main results of InAs MOSFET are: ohmic contact resistivity ρ_c = 5.10^-8Ω.cm^-2, III-V/high-k interface with  interface trap density D_it  around 5.10¹²eV^-1cm^-2, an Equivalent Oxyde Thickness EOT of 1.9nm, a slope under the threshold of 90mV / dec and drain current I_D greater than 1A / mm. Finally, to overcome short channel effect, we fabricated using LS-MBE a bottom-up multi-gate MOSFET with I_D=300mA/mm, SS=100mV/dec and DIBL=50mV/V.

Fig. 6 : Electron microscopic image of a cross-section of an InAs UTB MOSFET.
InAs zones were made by localized selective MBE.

The increase of the power consumption (PC) of digital circuits is a factor limiting CMOS technology perspectives according to the roadmap defined by the Moore’s law. Currently, the main way to significantly reduce PC consists in decreasing the DC voltage of MOSFET transistors (Vdd). However, considering the theoretical limit of the subthreshold slope of conventional MOSFET, equal to 60mV/dec at room temperature, the reduction of Vdd results in a strong increase of the leakage current (Ioff) leading to the increase of PC. Therefore, it becomes necessary to develop MOSFET with lower subthreshold slope (SS<60mV/dec) such as TFET (Tunnel-FET) or I-MOSFET (Impact-ionization MOSFET) and able to work at low Vdd (<500mV) and high Ion currents (>1A/mm). Today, Silicon I-MOSFET shows very promising results in term of SS and Ion but Vdd is still too large (6.5V). A possible way, proposed in this activity, is the use of narrow bandgap materials coupled with a heterostructure bandgap engineering to reduce Vdd of I- MOSFET devices. This activity was funded and coordinated by ANR JCJC MOS35 and IEMN respectively. An optimization of the interface between the oxide and III-V semiconductor has been developed by an innovative treatment using oxygen plasma (O₂) to reduce interface trap density (Dit). This treatment has shown a clear improvement in charge control efficiency with a minimum Dit of 8. 10¹¹ eV^-1cm^-2 on Al₂O₃-InGaAs interface. GaSb based I-MOSFET (Fig. 7) have been fabricated. Minimum operating voltage is about 4.5V. Although this value is lower than that obtained on Silicon I-MOSFET, this one is still too large to be competitive with MOSFET technology.

Fig. 7 : GaSb I-MOSFET

The tunnel transistor, based on the electrostatic control of the band-to-band tunnel effect, is a solution to surpass the 60mV/dec limit. The antimony-based heterostructures are particularly well adapted since the large band offsets offered makes it possible to significantly improve the probabilities of the tunnel transitions and thus the current in the on-state of the transistor. The investigations took place in collaboration with EPIPHY group within the framework of ANR JCJC program. A co-supervised PhD student was recruited: Vinay Chinni. We thus explored the potential of the family of « 6.1 Å » materials (InAs, GaSb, AlGaSb). This device was never studied in the lab. A complete and original process of TFET InAs/AlGaSb has been developed. The fabrication process involved an anisotropic and selective wet chemical etching of the InAs channel to form a V-shaped mesa with lateral side gates (Fig. 8). This new architecture provided a large ON-current at room temperature while enabling an efficient pinch-off thanks to a reduced body thickness near the tunneling interface.

An InAs/Al_xGa_1−xSb near broken gap TFET on GaAs substrate has been fabricated and characterized. Vertical architecture together with a V-shaped mesa etching of the InAs channel down to 80 nm at the tunneling interface results in a large I_ON of 433 μA/um at V_DS=V_GS=0.5V. Low temperature measurements limiting the influence of traps lead to a minimum SS of 71 mV/decade together with a 40 μA.μm⁻¹ of ON current at V_DS = 0.1 V. Although the SS be still high the I_ON current is the better ever reported for a III-V TFET. These results however indicated that further improvements of the gate-oxide/semiconductor interface could lead to a valuable solution for ultra-low power logic.

Fig. 8 : Tunnel FET InAs/AlGaSb

The end of Moore’s law is paradoxically an opportunity to investigate new information processing paradigms. In this context, bio-inspired hardware is attracting more and more interest for analogue computing and adaptive information processing, because it allows a drastic reduction of energy consumption while showing cognitive properties.

The SPINE project (www.spine.univ-lille.fr) launched in 2015 by 4 IEMN scientists demonstrated the fabrication of an original artificial (patented) neuron with optimised energy efficiency and high flexibility in terms of spike amplitude and frequency. The neuron circuit uses a standard 65 nm CMOS industrial technology and different circuit versions have been fabricated (Fig. 9) either to closely mimic biological neurons or to exhibit higher spiking frequencies or even specific spiking modes such as bursts or tonic spiking (Fig. 10). The SPINE project is also developing a bio-inspired (patented) vision sensor and a (patented) plastic synapse technology that allows the design complete neural networks showing learning capabilities.

The most important feature of the developed approach is its ultra-low dissipated energy of a few femto-joules per spike, which improves prior state-of-the-art of the artificial neurons as well as the biological neuron performance by two to three orders of magnitude. This performance level is a key advantage to address various applications, such as highly integrated neuro-processors for robotics, neuroscience or medical applications such Parkinson disease or DMLA.

Fig. 9 : Artificial neuron circuit using TSMC
65nm CMOS technology

Fig. 10 : Electrical response of the artificial neuron
(green) to pulse current excitation (yellow)